BCD (Bipolar-CMOS-DMOS) process technologies include manufacturing steps to fabricate many different types of semiconductor device in the same silicon substrate. While a logic process may only need to provide NMOS and PMOS transistors, and a memory process may also need to support a small number of devices, BCD processes must provide area-efficient and rugged highside and lowside power transistors (such as LDMOS), logic and analog CMOS, level-shifting MOS transistors, and bipolar transistors. A BCD manufacturing process therefore typically incorporates more masking steps and total processing steps than other manufacturing processes at the same technology node. More process steps mean more expensive wafers. Masking steps are particularly expensive, and silicon foundries typically charge by number of masking steps, making wafer cost directly proportional to number of masking steps.
Two factors determine the cost of a silicon die (not including test and packaging cost, and neglecting the effect of manufacturing yield less than 100%): wafer cost and die size. The die cost is equal to wafer cost divided by die per wafer. Therefore, to minimize die cost, it is important to minimize die area by using small design rules and area-efficient devices, and it is also important to minimize wafer cost by reducing the number of masking steps in the manufacturing process. Many BCD products consist of large power transistors which occupy most of the die area, and other circuitry which occupies a relatively small portion of the total die area. In a case like this, die cost can be minimized by eliminating masking steps that are not necessary for the construction of area-efficient and robust power transistors, and accepting somewhat larger area dedicated to non-power devices. If power transistors take up enough of the die area, the increase in die area is small enough that die cost is also reduced.
Besides masking steps, another processing step that significantly contributes to wafer cost is epitaxial growth (“epi”). Removing epi from a BCD process with lateral power transistors is feasible in a modern manufacturing line with high-energy ion implantation equipment. Without epi, certain analog components (notably vertical NPN and lateral PNP transistors) may have poorer performance and/or larger size than with epi, but this is a good compromise to make if most of the die area is occupied by power transistors.
From the foregoing discussion it can be concluded that an invention which reduces the number of masking steps and eliminates the need for epitaxial deposition, while not adversely affecting power transistor size or robustness, would be useful to a manufacturer of power integrated circuits.